module clint (
    input   clk,
    input   reset,

    input  req,
    input [63:0]  addr,
    input  wr,
    input  wstrb,
    input [63:0] wdata,
    output clint_data_ok,
    output time_int ,
    output [63:0] clint_rdata 
);

reg  [63:0] mtime;
reg  [63:0] mtimecmp;
reg         tick;
reg         data_ok;
reg         sel_cmp;

wire  mtime_we;
wire  cmp_we;
wire  is_cmp;
wire  is_mtime;

always @( posedge clk) begin
    data_ok <= (is_cmp || is_mtime) && req;
    sel_cmp <= is_cmp;   
end
assign is_cmp = addr == 64'h0000_0000_0200_4000;
assign is_mtime= addr == 64'h0000_0000_0200_bff8;
assign clint_data_ok = data_ok;
assign cmp_we = req && wr && is_cmp;
assign mtime_we =  req && wr && is_mtime;
//////mtime//////

always @(posedge clk) begin
    if (reset) tick <= 1'b0;
        else tick <= ~tick;
    if (mtime_we) begin
        mtime <= wdata;
    end
    else if (tick) begin
        mtime <= mtime + 1'b1;
    end
    
end
//////mtimecmp////
always @(posedge clk) begin
    if (cmp_we)
        mtimecmp <= wdata;
end

assign time_int = mtime >=  mtimecmp;
assign clint_rdata = is_cmp ? mtimecmp : mtime;



endmodule